The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method for reducing oxidation encroachment of stacked gate layer.
Memory technology has progressed considerably in recent years. Since the operational speed and the manipulation data amount of a central processing unit (CPU) is increasing, the performance of a memory cell is increasing at the same time. For example, high speed erasing is a popular method for improving the performance of a memory. Volatile storage memories, such as random access memories (RAM), are widely used in computer nowadays. However, the stored data in RAM vanishes while the power is broke off. Another nonvolatile storage memories, such as mask read only memory (Mask ROM), erasable programmable ROM (EPROM), or electrically erasable programmable ROM (EEPROM) will not lost the stored messages when power dismissed and will be better for some specific usage.
Flash memories are also a nonvolatile storage memory, which has similar structure than conventional EEPROMs. They have a very high erasing speed feature in either an overall region or a local region thereof, and therefore they are very popularly applied in the computer field. For example, they are used to replace the read-only memories to store the firmware such as BIOS (basic input/output system). The users can easily update their BIOS by rewriting the flash memory.
Conventional flash memory cells have a double or triple layer of polysilicon structure. The first polysilicon layer is patterned to form the floating gates, and the second polysilicon layer is patterned to form the control gates and the word lines structure. A third polysilicon layer is patterned as select gates to form the triple layer polysilicon structure.
In the process of fabricating flash memory cells, the first polysilicon layer is patterned by photolithography and etching technology to form a plurality of parallel lines. The second polysilicon layer is subsequently formed and patterned to form a plurality of parallel lines that served as the control gates and the structure of the word lines which is perpendicular to the first polysilicon lines. While forming the control gates, the portion of underlying first polysilicon lines between two word lines is also removed until exposing the substrate to form the floating gates. However, in the procedure of etching the first polysilicon lines, since the anisotropic etching limitation, the removed portion of the first polysilicon lines is not completed and portion of the polysilicon is remained on the sidewall of the insulating layer. This results in circuit short between word lines because of the polysilicon residue connection, and therefore data can not be access to the memory. In order to eliminating polysilicon residue, a conventional method is achieved by thermal oxidization treatment to convert polysilicon residue into silicon dioxide. Although the polysilicon residue can be eliminated, exposed edge portions of the first and second polysilicon layers are also encroached in the long time thermal oxidation treatment process, so that the thickness of the edge portion of ONO layer between the first and second polysilicon layers are increased. The increased thickness of the ONO layer reduces the capacitance coupling ratio between the control gate and floating gate, electron trapping capability of the floating gate is decreased and thereby affecting the operation performance of the flash memory.
The present invention provides a method for reducing oxidation encroachment of stacked gate layer by implanting nitrogen ions into sidewall surface of the stacked gate layer to reduce the oxidation rate to the stacked gate layer. The present invention also provides enough time to eliminate polysilicon residue under less oxidation encroachment of the stacked gate layer, and increases process window of oxidation process.
The present invention provides a method for reducing oxidation encroachment of stacked gate layer. The method comprises the following steps. A titled ion implantation step is performed to implant nitrogen ions into the sidewall surface of the polysilicon layer. An oxygen-annealing step is then performed to form a silicon oxynitride layer on the sidewall of the polysilicon layer.
The present invention also provides a method of fabricating a semiconductor memory device. The method at least comprises the following steps. A gate oxide layer, a first polysilicon layer and a nitride layer are formed on a semiconductor substrate, and the nitride layer, the first polysilicon layer and the gate oxide layer are then patterned to form desired pattern. An insulating layer is formed over the semiconductor substrate. A portion of the insulating layer is removed until exposing the nitride layer, and the nitride layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer and adjacent portion of the insulating layer. A dielectric layer, a third polysilicon layer and a conductive layer are formed over the semiconductor substrate. The conductive layer, the third polysilicon layer, the dielectric layer, the second polysilicon layer and the first polysilicon layer to form a plurality of parallel stacked gate layers. A tilted ion implantation step is performed to implant nitrogen ions into the sidewall surface of the stacked gate layers. An oxygen-annealing step is then performed to form a silicon oxynitride layer on the sidewall surface of the stacked gate layers.